A conventional semiconductor package (semiconductor device) having a substrate for mounting a semiconductor element (wiring board) is manufactured by laminating a photosensitive coverlay film with a thickness of 30 μm to be an insulating coating (insulating film) on the connection land side of the substrate, opening external connection terminals by development, and electrolessly plating the surface of the wiring conductor sequentially with nickel, palladium and gold (refer to Japanese Patent Application Laid-Open No. 2002-261186 (FIG. 1)).